Thursday, June 13, 2002, 2:00 PM - 4:00 PM | Room: Auditorium B SESSION 46    SPECIAL SESSION: Designing SoCs for Yield Improvement    Chair: Srivaths Ravi - NEC USA, Princeton, NJ    Organizers: Anand Raghunathan, Alfred E Dunlop    The increasing scale and complexity of System-on-Chips, together with the emergence of new failure mechanisms in nanometer technologies, poses serious challenges to various steps of the SoC manufacturing process, including manufacturing test, defect diagnosis, yield enhancement, and reliability improvement. Conventional approaches to address these issues are giving way to solutions that increasingly involve special IP blocks embedded in the SoCs (called infrastructure IP) to help with the above steps. The first presentation will focus on how infrastructure IPs can be used to address various manufacturing challenges, ranging from manufacturing test and silicon debug to improving yield and reliability. The second presentation addresses a recent and growing trend in SoCs - the use of embedded reconfigurable logic. It covers the self-test, diagnosis, and repair for yield improvement of embedded FPGAs, and outlines how they can be used to test other embedded cores.      46.1 Embedding Infrastructure IP for SoC Yield Improvement    Speaker(s): Yervant Zorian - Virage Logic, Fremont, CA    Author(s): Yervant Zorian - Virage Logic, Fremont, CA      46.2 Using Embedded FPGAs for SoC Yield Improvement    Speaker(s): Miron Abramovici - Agere Systems, Inc., Murray Hill, NJ    Author(s): Miron Abramovici - Agere Systems, Inc., Murray Hill, NJ Charles Stroud - Univ. of North Carolina, Charlotte, NC Marty Emmert - Wright State Univ., Dayton, OH